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cy14v101la cy14v101na 1-mbit (128 k 8/64 k 16) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53953 rev. *j revised july 24, 2013 1-mbit (128 k 8/64 k 16) nvsram features 25 ns and 45 ns access times internally organized as 128 k 8 (cy14v101la) or 64 k 16 (cy14v101na) hands off automatic store on power down with only a small capacitor store to quantumtrap non-volatile elements initiated by software, device pin, or autostore on power down recall to sram initiated by software or power up infinite read, write, and recall cycles 1 million store cycles to quantumtrap 20 year data retention core v cc = 3.0 v to 3.6 v; i/o v ccq = 1.65 v to 1.95 v industrial temperature 48-ball fine-pitch ball grid array (fbga) package pb-free and restriction of hazardous substances (rohs) compliance functional description the cypress cy14v101la/cy14v101na is a fast static ram, with a non-volatile element in each memory cell. the memory is organized as 128 k bytes of 8 bits each or 64 k words of 16 bits each. the embedded non-volatile elements incorporate quantumtrap technology, producing the world?s most reliable non-volatile memory. the sram provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the non-volatile elements (the store operation) takes place automatically at power down. on power-up, data is restored to the sram (the recall operat ion) from the non-volatile memory. both the store and recall operations are also available under software control. static ram array 1024 x 1024 r o w d e c o d e r column i/o column dec i n p u t b u f f e r s power control store/recall control quatrum trap 1024 x 1024 store recall v cc v cap hsb a 0 a 1 a 2 a 3 a 4 a 10 a 11 software detect a 14 - a 2 oe ce we bhe ble a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 logic block diagram [1, 2, 3] v ccq notes 1. address a 0 ?a 16 for 8 configuration and address a 0 ?a 15 for 16 configuration. 2. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 3. bhe and ble are applicable for 16 configuration only.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 2 of 22 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 device operation .............................................................. 4 sram read ................................................................ 4 sram write ................................................................. 4 autostore operation .................................................... 4 hardware store operation ....................................... 4 hardware recall (power-up) .................................. 5 software store ......................................................... 5 software recall ....................................................... 5 preventing autostore .................................................. 6 data protection ............................................................ 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test loads .................................................................. 9 ac test conditions .......................................................... 9 ac switching characteristics ....................................... 10 sram read cycle .................................................... 10 sram write cycle ..................................................... 10 switching waveforms .................................................... 10 autostore/power-up recall ....................................... 13 switching waveforms .................................................... 13 software controlled store/recall cycle ................ 14 switching waveforms .................................................... 14 hardware store cycle ................................................. 15 switching waveforms .................................................... 15 truth table for sram operations ................................ 16 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community ................................. 22 technical support ................. .................................... 22
cy14v101la cy14v101na document number: 001-53953 rev. *j page 3 of 22 pinouts figure 1. 48-ball fbga pinout we v ccq a 11 a 10 v cap a 6 a 0 a 3 ce nc nc dq 0 a 4 a 5 nc dq 2 dq 3 nc v ss a 9 a 8 oe v ss a 7 nc nc v cc nc a 2 a 1 nc v ccq dq 4 nc dq 5 dq 6 nc dq 7 nc a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 nc nc dq 1 (not to scale) top view ( 8) [6] we v ccq a 11 a 10 v cap a 6 a 0 a 3 ce dq 10 dq 8 dq 9 a 4 a 5 dq 13 dq 12 dq 14 dq 15 v ss a 9 a 8 oe v ss a 7 dq 0 bhe v cc nc a 2 a 1 ble v ccq dq 2 dq 1 dq 3 dq 4 dq 5 dq 6 dq 7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h nc nc nc dq 11 (not to scale) top view ( 16) [6] [4] [5] [4] [5] pin definitions pin name i/o type description a 0 ?a 16 input address inputs. used to select one of the 131,072 byte s of the nvsram for 8 configuration. a 0 ?a 15 address inputs. used to select one of the 65,536 words of the nvsram for 16 configuration. dq 0 ?dq 7 input/output bidirectional data i/o lines for 8 configuration. us ed as input or output li nes depending on operation. dq 0 ?dq 15 bidirectional data i/o lines for 16 configuration. used as input or output lines depending on operation. we input write enable input, active lo w. when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low. when low, se lects the chip. when high, deselects the chip. oe input output enable, active low. the active low oe input enables the data out put buffers during read cycles. i/o pins are tri-stated on deasserting oe high. bhe input byte high enable, active low. controls dq 15 ?dq 8 . ble input byte low enable, active low. controls dq 7 ?dq 0 . v ss ground ground for the device. must be connected to the ground of the system. v cc power supply power supply inputs to the core of the device. v ccq power supply power supply inputs for the inputs and outputs of the device. hsb input/output hardware store busy (hsb ). output: indicates busy status of nvsram when low. after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keeps this pin high (external pull-up resistor connection optional). input: hardware store implemented by pulling this pin low externally. v cap power supply autostore capacitor. supplies power to the nvsram during power loss to store data from sram to non-volatile elements. nc no connect no connect. this pin is not connected to the die. notes 4. address expansion for 2-mbit . nc pin not connected to die. 5. address expansion for 4-mbit . nc pin not connected to die. 6. address expansion for 8-mbit . nc pin not connected to die.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 4 of 22 device operation the cy14v101la/cy14v101na nvsram is made up of two functional components paired in the same physical cell. they are an sram memory cell and a non-volatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the non-volatile cell (the store operation), or from the non-vo latile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and writ e operations are inhibited. the cy14v101la/cy14v101na supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the non-volatile cells and up to 1 million store operations. refer to the truth table for sram operations on page 16 for a complete description of read and write modes. sram read the cy14v101la/cy14v101na performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0?16 or a 0?15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit word s. when the read is initiated by an address transition, the output s are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?15 are written into the memory if the data is valid t sd before the end of a we -controlled write or before the end of a ce -controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit words. keep oe high during the entire write cycle to avoi d data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14v101la/cy14v101na stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb ; software store activated by an address sequence; autostore on device power down. the autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14v101la/cy14v101na. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if a capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 6 . if autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient charge to complete the store. this corrupts the data stored in nvsram. figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 7 for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. place a pull-up on we to hold it inactive during power up. this pull-up is only effective if the we signal is tristate during power up. many mpus tristate their controls on power-up. this mu st be verified when using the pull-up. when the nvsram comes out of power-on-recall, the mpu mu st be active or the we held inactive until the mp u comes out of reset. to reduce unnecessary non-volatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. figure 2. autostore mode hardware store operation the cy14v101la/cy14v101na provides the hsb pin to control and acknowledge the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14v101la/cy14v101na conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiated. however, any sram write 0.1 uf v cc 10 kohm v cap we v cap v ss v ccq v ccq v cc 0.1 uf
cy14v101la cy14v101na document number: 001-53953 rev. *j page 5 of 22 cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14v101la/cy14v101na. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, rega rdless of how it is initiated, the cy14v101la/cy14v101na c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power up or after any low power condition (v cc cy14v101la cy14v101na document number: 001-53953 rev. *j page 6 of 22 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is reenabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or reenabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power down cycles. the part comes from th e factory with autostore enabled and 0x00 written in all cells. data protection the cy14v101la/cy14v101na protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14v101la/cy14v101na is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). when v ccq < v iodis, i/os are disabled (no store takes place). this protects aga inst inadvertent writes during brown out conditions on v ccq supply. l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [10] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram non-volatile store output data output data output data output data output data output high z active i cc2 [10] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram non-volatile recall output data output data output data output data output data output high z active [10] table 1. mode selection (continued) ce we oe bhe , ble [7] a 15 ?a 0 [8] mode i/o power note 10. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a non-volatile cycle.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 7 of 22 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time: at 150 ? c ambient temperature ..................... 1000 h at 85 ? c ambient temperature .................... 20 years maximum junction temperature ................................. 150 ? c supply voltage on v cc relative to v ss ...........?0.5 v to 4.1 v supply voltage on v ccq relative to v ss ......?0.5 v to 2.45 v voltage applied to outputs in high z state ..................................?0.5 v to v ccq + 0.5 v input voltage .....................................?0.5 v to v ccq + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ...............?2.0 v to v ccq + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .................................. 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current .................................................... > 140 ma operating range range ambient temperature v cc v ccq industrial ?40 ? c to +85 ? c 3.0 v to 3.6 v 1.65 v to 1.95 v dc electrical characteristics over the operating range parameter description test conditions min typ [11] max unit v cc power supply voltage 3.0 3.3 3.6 v v ccq 1.65 1.8 1.95 v i cc1 average v cc current t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) ??70ma ??52ma i ccq1 average v ccq current ? ? 25 ma ??15ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc(typ) , 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma) ?35?ma i ccq3 average v ccq current at t rc = 200 ns, v ccq(typ) , 25 c ?5?ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??8ma i sb v cc standby current ce > (v ccq ? 0.2 v). v in < 0.2 v or > (v ccq ? 0.2 v). standby current level after non-volatile cycle is complete. inputs are static. f = 0 mhz ??8ma i ix [12] input leakage current (except hsb ) v ccq = max, v ss < v in < v ccq ?1 ? +1 a input leakage current (for hsb )v ccq = max, v ss < v in < v ccq ?100 ? +1 a notes 11. typical values are at 25 c, v cc = v cc(typ) and v ccq = v ccq(typ) . not 100% tested. 12. the hsb pin has i out = ?4 a for v oh of 1.07 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 8 of 22 i oz off-state output leakage current v ccq = max, v ss < v out < v ccq , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 ? +1 a v ih input high voltage ? 0.7 v ccq ?v ccq + 0.3 v v il input low voltage ? ? 0.3 ? 0.3 v ccq v v oh output high voltage i out = ?1 ma v ccq ? 0.45 ? ? v v ol output low voltage i out = 2 ma ? ? 0.45 v v cap [13] storage capacitor between v cap pin and v ss 61 68 180 f v vcap [14, 15] maximum voltage driven on v cap pin by the device v cc = max ? ? v cc v data retention and endurance parameter description min unit data r data retention 20 years nv c non-volatile store operations 1,000 k capacitance parameter [14] description test conditions max unit c in input capacitance (except bhe , ble and hsb ) t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) , v ccq = v ccq(typ) 7pf input capacitance (for bhe , ble and hsb ) 8pf c out output capacitance (except hsb )7pf output capacitance (for hsb ) 8pf thermal resistance parameter [14] description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 48.19 ? c/w ? jc thermal resistance (junction to case) 6.5 ? c/w dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [11] max unit notes 13. min v cap value guarantees that there is a sufficient charge availabl e to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycl e so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. refer application note an43593 for more details on v cap options. 14. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage. 15. these parameters are guaranteed by design and are not tested.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 9 of 22 ac test conditions input pulse levels.................................................0 v to 1.8 v input rise and fall times (10% to 90%)...................... < 1.8 ns input and output timing reference levels........................ 0.9 v ac test loads figure 3. ac test loads 1.8 v output 5 pf r1 r2 450 ? 1.8 v output 30 pf r1 r2 450 ? for tri-state specs 450 ? 450 ?
cy14v101la cy14v101na document number: 001-53953 rev. *j page 10 of 22 ac switching characteristics over the operating range parameters [16] description 25 ns 45 ns unit cypress parameters alt parameters min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 45 ns t rc [17] t rc read cycle time 25 ? 45 ? ns t aa [18] t aa address access time ? 25 ? 45 ns t doe t oe output enable to data valid ? 12 ? 20 ns t oha [18] t oh output hold after address change 3 ? 3 ? ns t lzce [19, 20] t lz chip enable to output active 3 ? 3 ? ns t hzce [19, 20] t hz chip disable to output inactive ? 10 ? 15 ns t lzoe [19, 20] t olz output enable to output active 0 ? 0 ? ns t hzoe [19, 20] t ohz output disable to output inactive ? 10 ? 15 ns t pu [19] t pa chip enable to power active 0 ? 0 ? ns t pd [19] t ps chip disable to power standby ? 25 ? 45 ns t dbe[ [19] ? byte enable to data valid ? 12 ? 20 ns t lzbe [19] ? byte enable to output active 0 ? 0 ? ns t hzbe [19] ? byte disable to output inactive ? 10 ? 15 ns sram write cycle t wc t wc write cycle time 25 ? 45 ? ns t pwe t wp write pulse width 20 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 30 ? ns t sd t dw data setup to end of write 10 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? ns t hzwe [19, 20, 21] t wz write enable to output disable ? 10 ? 15 ns t lzwe [19, 20] t ow output active after end of write 3 ? 3 ? ns t bw ? byte enable to end of write 20 ? 30 ? ns switching waveforms figure 4. sram read cycle #1 (address controlled) [17, 18, 22] address data output address valid previous data valid output data valid t rc t aa t oha notes 16. test conditions assume signal transition time of 1.8 ns or less, timing reference levels of v ccq /2, input pulse levels of 0 to v cc q(typ) , and output loading of the specified i ol /i oh and load capacitance shown in figure 3 on page 9 . 17. we must be high during sram read cycles. 18. device is continuously selected with ce , oe and bhe / ble low. 19. these parameters are guaranteed by design and are not tested. 20. measured 200 mv from steady state output voltage. 21. if we is low when ce goes low, the outputs remain in the high-impedance state. 22. hsb must remain high during read and write cycles.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 11 of 22 figure 5. sram read cycle #2 (ce and oe controlled) [23, 24, 25] figure 6. sram write cycle #1 (we controlled) [23, 25, 26, 27] switching waveforms (continued) address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce notes 23. bhe and ble are applicable for 16 configuration only. 24. we must be high during sram read cycles. 25. hsb must remain high during read and write cycles. 26. if we is low when ce goes low, the outputs remain in the high impedance state. 27. ce or we must be > v ih during address transitions.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 12 of 22 figure 7. sram write cycle #2 (ce controlled) [28, 29, 30, 31] figure 8. sram write cycle #3 (bhe and ble controlled) [28, 29, 30, 31] switching waveforms (continued) data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe notes 28. bhe and ble are applicable for x16 configuration only. 29. hsb must remain high during read and write cycles. 30. if we is low when ce goes low, the outputs remain in the high impedance state. 31. ce or we must be > v ih during address transitions.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 13 of 22 autostore/power-up recall over the operating range parameter description cy14v101la/cy14v101na unit min max t hrecall [32] power-up recall duration ? 20 ms t store [33] store cycle duration ? 8 ms t delay [34] time allowed to comple te sram write cycle ? 25 ns v switch low voltage trigger level for v cc ?2.90v v iodis [35] i/o disable voltage on v ccq ?1.50v t vccrise [36] v cc rise time 150 ? s v hdis [36] hsb output disable voltage on v cc ?1.9v t lzhsb [36] hsb to output active time ? 5 s t hhhd [36] hsb high active time ? 500 ns switching waveforms figure 9. autostore or power-up recall [37] v iodis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited ( rwi ) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note v switch v hdis read & write brown out i/o disable v cc v cc v ccq v ccq v ccq note 33 33 38 38 notes 32. t hrecall starts from the time v cc rises above v switch . 33. if an sram write has not taken place si nce the last non-volatile cycle, no autostore or hardware store takes place. 34. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 35. hsb is not defined below v iodis voltage. 36. these parameters are guaranteed by design and are not tested. 37. read and write cycles are ignored during store, recall, and while v cc is below v switch . 38. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 14 of 22 software controlled store/recall cycle over the operating range parameters [39, 40] description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 ? 45 ? ns t sa address setup time 0 ? 0 ? ns t cw clock pulse width 20 ? 30 ? ns t ha address hold time 0 ? 0 ? ns t recall recall duration ? 200 ? 200 s switching waveforms figure 10. ce and oe controlled software store/recall cycle [40] figure 11. autostore enable / disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note 41 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note 41 notes 39. the software sequence is clocked with ce controlled or oe controlled reads. 40. the six consecutive addresses must be read in the order listed in table 1 on page 5 . we must be high during all six consecutive cycles. 41. dq output data at the sixth read may be invalid since the output is disabled at t delay time.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 15 of 22 hardware store cycle over the operating range parameters description cy14v101la/cy14v101na unit min max t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns t ss [42, 43] soft sequence processing time ? 100 ? s switching waveforms figure 12. hardware store cycle [44] figure 13. soft sequence processing [42, 43] ~ ~ ~ ~ hsb (in) hsb (out) so rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t dhsb t dhsb t phsb hsb pin is driven high to v ccq only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 42. this is the amount of time it takes to take action on a soft sequence command. v cc and v ccq power must remain high to effectively register command. 43. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. 44. if an sram write has not taken place since the last non-volatile cycle, no autostore or hardware store takes place.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 16 of 22 truth table for sram operations hsb must remain high for sram operations. table 2. truth table for 8 configuration ce we oe inputs/outputs [45] mode power h x x high z deselect / power-down standby l h l data out (dq 0 ?dq 7 ) read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ) write active table 3. truth table for 16 configuration ce we oe bhe [46] ble [46] inputs/outputs [45] mode power h x x x x high z deselect / power-down standby l x x h h high z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z read active l h l l h data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z read active l h h l l high z output disabled active l h h h l high z output disabled active l h h l h high z output disabled active llxlldata in (dq 0 ?dq 15 )write active llxhldata in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z write active llxlhdata in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z write active notes 45. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 46. bhe and ble are applicable for 16 configuration only.
cy14v101la cy14v101na document number: 001-53953 rev. *j page 17 of 22 ordering information ordering code definitions speed (ns) ordering code package diagram package type operating range 25 cy14v101la-ba25xit 51-85128 48-ball fbga industrial cy14v101la-ba25xi CY14V101NA-BA25XIt CY14V101NA-BA25XI 45 cy14v101la-ba45xit cy14v101la-ba45xi cy14v101na-ba45xit cy14v101na-ba45xi all parts are pb-free. the above table contains final informati on. contact your local cypress sales representative for availabi lity of these parts. option: t - tape and reel blank - std. speed: 25 - 25 ns 45 - 45 ns data bus: l - 8 n - 16 density: 101 - 1 mb voltage: v - 3.3 v v cc , 1.8 v v ccq cypress cy 14 v 101 l a - ba 25 x i t 14 - nvsram pb-free package: ba - 48-ball fbga temperature: i - industrial (?40 to 85 c) die revision: blank - no rev a - 1 st rev
cy14v101la cy14v101na document number: 001-53953 rev. *j page 18 of 22 package diagrams figure 14. 48-ball fbga (6 10 1.2 mm) ba48b package outline, 51-85128 51-85128 *f
cy14v101la cy14v101na document number: 001-53953 rev. *j page 19 of 22 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array hsb hardware store busy i/o input/output nvsram non-volatile static random access memory oe output enable sram static random access memory rohs restriction of hazardous substances rwi read and write inhibited we write enable symbol unit of measure c degree celsius k ? kilohm ? a microampere ma milliampere mm millimeter ? f microfarad mhz megahertz ? s microsecond ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy14v101la cy14v101na document number: 001-53953 rev. *j page 20 of 22 document history page document title: cy14v101la/cy14v101na, 1-mbit (128 k 8/64 k 16) nvsram document number: 001-53953 rev. ecn no. orig. of change submission date description of change ** 2729117 gvch / aesa 07/02/09 new data sheet. *a 2765890 gvch 09/18/09 removed commercial temperature related specs changed part number from cy14a101l/cy14a101n to cy14v101la/cy14v101na removed 20 ns access speed specs figure 3: updated autostore mode page 4; updated hardware store (hsb ) operation description page 5; updated software store operation description added i ccq1 and i ccq3 for v ccq operation updated v ih /v il as 70%/30% of v ccq updated v oh test condition updated footnote 24 and added footnote 25, 30 updated v iodis parameter value from 1.6 v to 1.5 v updated footnote 10 added contents on page 2 *b 2767333 gvch / pyrs 01/06/10 removed 44-tsop ii package related specs changed latch up current from 200 ma to 140 ma changed store cycles to quantumtrap from 200 k to 1 million added contents *c 2923525 gvch 04/27/10 pin definitions : added more clarity on hsb pin operation hardware store operation : added more clarity on hsb pin operation ta b l e 1 : added more clarity on status of bhe /ble pin operation updated hsb pin operation in figure 9 updated footnote 24 *d 2999981 gvch 08/04/2010 changed datasheet st atus from ?preliminary? to ?final? *e 3033088 gvch 09/22/2010 changed i sb and i cc4 value from 5 ma to 8 ma added acronyms and units of measure table updated as per new template *f 3123639 gvch 12/30/2010 removed note ?address expans ion for 16 mbit. nc pin not connected to die.? in page 3 as 16 mb address expansion is not supported in 48-ball fbga pack- age. added cy14v101la-ba25xi and CY14V101NA-BA25XI parts in ordering information . *g 3150308 gvch 01/21/2011 updated input capacitance for bhe and ble pin updated input and output capacitance for hsb pin updated ordering information *h 3301833 gvch 07/04/2011 updated dc electrical characteristics (added note 13 and referred the same note in v cap parameter). updated ac switching characteristics (added note 16 and referred the same note in parameters). updated thermal resistance (values of ? ja and ? jc for 48-ball fbga package). updated package diagrams . *i 3759015 gvch 09/28/2012 removed best practices. updated maximum ratings (removed ?ambient temperature with power applied? and included ?maximum junction temperature?). updated dc electrical characteristics (added v vcap parameter and its details, added note 14 and referred the same note in v vcap parameter, also referred note 15 in v vcap parameter).
cy14v101la cy14v101na document number: 001-53953 rev. *j page 21 of 22 *j 4075544 gvch 07/24/2013 updated pin definitions : updated description of hsb pin (added more clarity). updated device operation : updated autostore operation (removed sentence ?the hsb signal is monitored by the system to detect if an autostore cycle is in progress.?). updated in new template. completing sunset review. document history page (continued) document title: cy14v101la/cy14v101na, 1-mbit (128 k 8/64 k 16) nvsram document number: 001-53953 rev. ecn no. orig. of change submission date description of change
document number: 001-53953 rev. *j revised july 24, 2013 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14v101la cy14v101na ? cypress semiconductor corporation, 2009-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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